Non-planar transistors which utilize a body of semiconductor material protruding from a substrate surface employ a gate electrode that wraps around two, three, or even all sides of the semiconductor body (i.e., dual-gate, tri-gate, nanowire transistors, respectively). Source and drain regions are formed in the body, or as re-grown portions coupled to the body, on either side of the gate electrode.
With the introduction of high-k gate dielectrics, reliable gate control of a semiconductor channel region between the source and drain regions is difficult to achieve for non-planar devices even where the channel semiconductor is silicon. For a group III-V FET, which employs a III-V compound semiconductor for a transistor channel region, gate control is all the more elusive. The metal-oxide-semiconductor (MOS) interfaces associated such materials are much less studied than their silicon counterparts, and much less well-behaved (e.g., suffering poor quality native oxides, sub-stoichiometric surfaces, etc.).